The memory usually refers to a form of the semiconductor device for information retention. Specifically, there are two types of memories, namely the volatile memory and the non-volatile memory, based on their capability of data storage and the existence of electrical power. For instance, the volatile memory such as the random access memory (RAM) requires power to maintain the stored information.
The dynamic random access memory (DRAM) is one type of RAM that stores each bit of data in a separate capacitor within an integrated circuit. Since real capacitors leak charge, the stored information eventually fades away unless the capacitor charge is refreshed periodically.
When a DRAM is in power-on status, millions of capacitors in the DRAM are charged from a voltage level of zero to a certain value (say 1.3 volts) simultaneously. At this moment, the DRAM consumes current. Please refer to FIG. 1, which is a time versus current diagram during a power-on period of a DRAM. It can be observed that there is an ultimate value of the current variation, which is called the peak current.
Unfortunately, if the value of the peak current exceeds that of the maximum loading defaulted by the system, the power-on process of the system will fail. To overcome such an issue, there exists a power-on circuit designed for reducing the peak current.
FIG. 2 shows a schematic diagram of a power-on circuit in the prior art. The technical feature for the power-on circuit is to turn on/off those electronic devices in a DRAM sequentially. According to FIG. 2, a power-on circuit 2 includes an external power-on voltage detector 21, an internal power-on voltage detector 22, a voltage control circuit 23, and a plurality of electric pumps 24 for escalating the voltage level. There are four electric pumps 24 in this particular case. Next, a fast power-on process for the conventional DRAM is described below.
When an external voltage A is applied to the external power-on voltage detector 21, the external power-on voltage detector 21 generates a first control signal inite_n having a logical high state if the external voltage A is higher than a first threshold voltage (say 1 volt) defaulted in the external power-on voltage detector 21. The internal power-on voltage detector 22, which is coupled to the external power-on voltage detector, receives the first control signal inite_n and generates a second control signal on_vint having a logical high state, which is operable by the internal circuit. It is to be noted that there is a pre-determined time-delay (about 1 micro second) between the timing of the logical high state for the first control signal inite_n and that of the logical high state for the second control signal on_vint. Subsequently, the voltage control circuit 23, which is coupled to the internal power-on voltage detector 22, receives the second control signal on_vint and generates an enabling signal run_vpp.
During a fast power-on period for DRAM, when the enabling signal run_vpp is escalated to a logical high state, all those electric pumps 24 in the power-on circuit 2 are on. The electric pumps 24 are switching devices, each of which has several capacitors for storing electric power and for producing a higher voltage power source. However, the above-mentioned power-on circuit 2 for reducing the peak current may produce an unexpected amount of the peak current.
There exists a strategy for resolving the issue of peak current due to turning on all the electric pumps simultaneously, which is to turn on one electric pump while keeping others off during a slow power-on period and release the latter afterwards. Such a strategy may avoid the large amount of peak current due to turning on all the electric pumps simultaneously; nevertheless, the process for completing the charging to all the electric pumps takes more than 200 micro seconds which is defined as the minimum time period for the DRAM power-on sequence by JEDEC standards.
Therefore, it is necessary to provide a power-on management circuit for the memory to overcome the drawbacks in the prior art.